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M28C64
64 Kbit (8K x 8) Parallel EEPROM With Software Data Protection
s
Fast Access Time: - 90 ns at VCC=5 V for M28C64 and M28C64-A - 120 ns at VCC=3 V for M28C64-xxW
s
Single Supply Voltage: - 4.5 V to 5.5 V for M28C64 and M28C64-A - 2.7 V to 3.6 V for M28C64-xxW
28
s s
Low Power Consumption Fast BYTE and PAGE WRITE (up to 64 Bytes) - 1 ms at VCC=4.5 V for M28C64-A - 3 ms at VCC=4.5 V for M28C64 - 5 ms at VCC=2.7 V for M28C64-xxW
1
PDIP28 (BS)
PLCC32 (KA)
s
Enhanced Write Detection and Monitoring: - Ready/Busy Open Drain Output - Data Polling - Toggle Bit - Page Load Timer Status
1 28
s s s s
JEDEC Approved Bytewide Pin-Out Software Data Protection 100000 Erase/Write Cycles (minimum) Data Retention (minimum): - 40 Years for M28C64 and M28C64-xxW - 10 Years for M28C64-A
SO28 (MS) 300 mil width
TSOP28 (NS) 8 x 13.4 mm
Figure 1. Logic Diagram
VCC
Table 1. Signal Names
13
A0-A12 DQ0-DQ7 W E G RB VCC VSS Address Input Data Input / Output Write Enable Chip Enable Output Enable Ready / Busy Supply Voltage
8 DQ0-DQ7
A0-A12
W E
M28C64 RB
G
VSS
Ground
AI01350C
June 2000
1/24
M28C64
Figure 2A. DIP Connections
RB A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 28 2 27 3 26 4 25 5 24 6 23 7 22 M28C64 8 21 9 20 10 19 11 18 12 17 13 16 14 15
AI01351C
Figure 2C. SO Connections
VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3 RB A12 A7 A6 A5 A4 A3 A2 A1 A0 DQ0 DQ1 DQ2 VSS 1 2 3 4 5 6 7 M28C64 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 VCC W NC A8 A9 A11 G A10 E DQ7 DQ6 DQ5 DQ4 DQ3
AI01353C
Note: 1. NC = Not Connected
Note: 1. NC = Not Connected
Figure 2B. PLLC Connections
RB DU VCC W NC A7 A12
Figure 2D. TSOP Connections
G A11 A9 A8 NC W VCC RB A12 A7 A6 A5 A4 A3 22 21 A10 E DQ7 DQ6 DQ5 DQ4 DQ3 VSS DQ2 DQ1 DQ0 A0 A1 A2
1 32 A6 A5 A4 A3 A2 A1 A0 NC DQ0 A8 A9 A11 NC G A10 E DQ7 DQ6
9
M28C64
25
28 1
M28C64
15 14
17 DQ1 DQ2 VSS DU DQ3 DQ4 DQ5
7
8
AI01354C
AI01352D
Note: 1. NC = Not Connected 2. DU = Do Not Use
Note: 1. NC = Not Connected
DESCRIPTION The M28C64 devices consist of 8192x8 bits of low power, parallel EEPROM, fabricated with STMicroelectronics' proprietary single polysilicon CMOS technology. The devices offer fast access time, with low power dissipation, and require a single voltage supply (5V or 3V, depending on the option chosen). The device has been designed to offer a flexible microcontroller interface, featuring both hardware
and software handshaking, with Ready/Busy, Data Polling and Toggle Bit. The device supports a 64 byte Page Write operation. Software Data Protection (SDP) is also supported, using the standard JEDEC algorithm.
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M28C64
Table 2. Absolute Maximum Ratings 1
Symbol TA T STG VCC VIO VI VESD Parameter Ambient Operating Temperature Storage Temperature Supply Voltage Input or Output Voltage Input Voltage Electrostatic Discharge Voltage (Human Body model) 2 Value -40 to 125 -65 to 150 -0.3 to VCC+1 -0.6 to VCC+0.6 -0.3 to 6.5 4000 Unit C C V V V V
Note: 1. Except for the rating "Operating Temperature Range", stresses above those listed in the Table "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. Refer also to the ST SURE Program and other relevant quality documents. 2. MIL-STD-883C, 3015.7 (100 pF, 1500 )
Figure 3. Block Diagram
RB E G W
VPP GEN
RESET
CONTROL LOGIC
X DECODE
A6-A12 (Page Address)
ADDRESS LATCH
64K ARRAY
A0-A5
ADDRESS LATCH
Y DECODE
SENSE AND DATA LATCH
I/O BUFFERS
PAGE LOAD TIMER STATUS TOGGLE BIT DATA POLLING
AI01355
DQ0-DQ7
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M28C64
Table 3. Operating Modes 1
Mode Stand-by Output Disable Write Disable Read Write Chip Erase E 1 X X 0 0 0 G X 1 X 0 1 V W X X 1 1 0 0 DQ0-DQ7 Hi-Z Hi-Z Hi-Z Data Out Data In Hi-Z
Note: 1. 0=VIL; 1=VIH; X = VIH or VIL; V=12V 5%.
SIGNAL DESCRIPTION The external connections to the device are summarized in Table 1, and their use in Table 3. Addresses (A0-A12). The address inputs are used to select one byte from the memory array during a read or write operation. Data In/Out (DQ0-DQ7). The contents of the data byte are written to, or read from, the memory array through the Data I/O pins. Chip Enable (E). The chip enable input must be held low to enable read and write operations. When Chip Enable is high, power consumption is reduced. Output Enable (G). The Output Enable input controls the data output buffers, and is used to initiate read operations. Write Enable (W). The Write Enable input controls whether the addressed location is to be read, from or written to.
Ready/Busy (RB). Ready/Busy is an open drain output that can be used to detect the end of the internal write cycle. DEVICE OPERATION In order to prevent data corruption and inadvertent write operations, an internal V CC comparator inhibits the Write operations if the VCC voltage is lower than VWI (see Table 4A and Table 4B). Once the voltage applied on the V CC pin goes over the VWI threshold (VCC>VWI), write access to the memory is allowed after a time-out tPUW, as specified in Table 4A and Table 4B. Further protection against data corruption is offered by the E and W low pass filters: any glitch, on the E and W inputs, with a pulse width less than 10 ns (typical) is internally filtered out to prevent inadvertent write operations to the memory.
Table 4A. Power-Up Timing1 for M28C64 (5V range) (TA = 0 to 70 C or -40 to 85 C or -40 to 125 C; VCC = 4.5 to 5.5 V)
Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation (once VCC VWI) Write Inhibit Threshold 3.0 Min. Max. 1 10 4.2 Unit s ms V
Note: 1. Sampled only, not 100% tested.
Table 4B. Power-Up Timing1 for M28C64-xxW (3V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
Symbol tPUR tPUW VWI Parameter Time Delay to Read Operation Time Delay to Write Operation (once VCC VWI) Write Inhibit Threshold 1.5 Min. Max. 1 15 2.5 Unit s ms V
Note: 1. Sampled only, not 100% tested.
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M28C64
Read The device is accessed like a static RAM. When E and G are low, and W is high, the contents of the addressed location are presented on the I/O pins. Otherwise, when either G or E is high, the I/O pins revert to their high impedance state. Write Write operations are initiated when both W and E are low and G is high. The device supports both W-controlled and E-controlled write cycles (as shown in Figure 11 and Figure 12). The address is latched during the falling edge of W or E (which ever occurs later) and the data is latched on the rising edge of W or E (which ever occurs first). After a delay, t WLQ5H, that cannot be shorter than the value specified in Table 10A to Table 10C, the internal write cycle starts. It continues, under internal timing control, until the write operation is complete. The commencement of this period can be detected by reading the Page Load Timer Status on DQ5. The end of the cycle can be detected by reading the status of the Data Polling and the Toggle Bit functions on DQ7 and DQ6. Page Write The Page Write mode allows up to 64 bytes to be written on a single page in a single go. This is achieved through a series of successive Write operations, no two of which are separated by more than the t WLQ5H value (as specified in Table 10A to Table 10C). All bytes must be located on the same page address (A12-A6 must be the same for all bytes). The internal write cycle can start at any instant after t WLQ5H. Once initiated, the write operation is internally timed, and continues, uninterrupted, until completion. As with the single byte Write operation, described above, the DQ5, DQ6 and DQ7 lines can be used to detect the beginning and end of the internally controlled phase of the Page Write cycle. Software Data Protection (SDP) The device offers a software-controlled writeprotection mechanism that allows the user to inhibit all write operations to the device. This can be useful for protecting the memory from inadvertent write cycles that may occur during periods of instability (uncontrolled bus conditions when excessive noise is detected, or when power supply levels are outside their specified values). By default, the device is shipped in the "unprotected" state: the memory contents can be freely changed by the user. Once the Software Data Protection Mode is enabled, all write commands are ignored, and have no effect on the memory contents. The device remains in this mode until a valid Software Data Protection disable sequence is received. The device reverts to its "unprotected" state. The status of the Software Data Protection (enabled or disabled) is represented by a non-
Figure 4. Software Data Protection Enable Algorithm and Memory Write
Write AAh in Address 1555h Page Write Timing (see note 1) Page Write Timing (see note 1) Write AAh in Address 1555h
Write 55h in Address 0AAAh
Write 55h in Address 0AAAh
Write A0h in Address 1555h
Write A0h in Address 1555h Write is enabled Physical Page Write Instruction Page Write (1 up to 64 bytes)
SDP is set
SDP Enable Algorithm
Write to Memory When SDP is SET
AI01356C
Note: 1. The most significant address bits (A12 to A6) differ during these specific Page Write operations.
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M28C64
Figure 5. Software Data Protection Disable Algorithm
Write AAh in Address 1555h
Write 55h in Address 0AAAh
Page Write Timing
Write 80h in Address 1555h
Write AAh in Address 1555h
Write 55h in Address 0AAAh
Write 20h in Address 1555h
Unprotected State
AI01357B
volatile latch, and is remembered across periods of the power being off. The Software Data Protection Enable command consists of the writing of three specific data bytes to three specific memory locations (each location being on a different page), as shown in Figure 4. Similarly to disable the Software Data Protection, the user has to write specific data bytes into six different locations, as shown in Figure 5. This complex series of operations protects against the chance of inadvertent enabling or disabling of the Software Data Protection mechanism. When SDP is enabled, the memory array can still have data written to it, but the sequence is more complex (and hence better protected from inadvertent use). The sequence is as shown in Figure 4. This consists of an unlock key, to enable the write action, at the end of which the SDP continues to be enabled. This allows the SDP to be enabled, and data to be written, within a single Write cycle (tWC). Software Chip Erase Using this function, available on the M28C64 but not on the M28C64-A or M28C64-xxW, the contents of the entire memory are erased (set to FFh) by holding Chip Enable (E) low, and holding Output Enable (G) at VCC+7.0V. The chip is cleared when a 10 ms low pulse is applied to the Write Enable (W) signal (see Figure 7 and Table 5 for details).
Status Bits The devices provide three status bits (DQ7, DQ6 and DQ5), and one output pin (RB), for use during write operations. These allow the application to use the write time latency of the device for getting on with other work. These signals are available on the I/O port bits DQ7, DQ6 and DQ5 (but only during programming cycle, once a byte or more has been latched into the memory) or continuously on the RB output pin. Data Polling bit (DQ7). The internally timed write cycle starts after tWLQ5H (defined in Table 10A to Table 10C) has elapsed since the previous byte was latched in to the memory. The value of the DQ7 bit of this last byte, is used as a signal
Figure 6. Status Bit Assignment
DQ7 DP
DQ6 TB
DQ5 PLTS
DQ4 Hi-Z
DQ3 Hi-Z
DQ2 Hi-Z
DQ1 Hi-Z
DQ0 Hi-Z
DP TB PLTS Hi-Z
= Data Polling = Toggle Bit = Page Load Timer Status = High impedance
AI02815
6/24
M28C64
Figure 7. Chip Erase AC Waveforms (M28C64 and M28C64-xxW)
tWHEH E
G
tGLWH W tELWL tWLWH2 tWHRH
AI01484B
throughout this write operation: it is inverted while the internal write operation is underway, and is inverted back to its original value once the operation is complete. Toggle bit (DQ6). The device offers another way for determining when the internal write cycle is completed. During the internal Erase/Write cycle, DQ6 toggles from '0' to '1' and '1' to '0' (the first read value being '0') on subsequent attempts to read any byte of the memory. When the internal write cycle is complete, the toggling is stopped, and the values read on DQ7-DQ0 are those of the addressed memory byte. This indicates that the device is again available for new Read and Write operations. Page Load Timer Status bit (DQ5). An internal timer is used to measure the period between successive Write operations, up to tWLQ5H (defined in Table 10A to Table 10C). The DQ5 line is held low to show when this timer is running (hence showing that the device has received one write operation, and is waiting for the next). The DQ5 line is held high when the counter has
overflowed (hence showing that the device is now starting the internal write to the memory array). Ready/Busy pin. The RB pin is an open drain output that is held low during the erase/write cycle, and that is released (allowed to float) at the completion of the programming cycle.
Table 5. Chip Erase AC Characteristics1 for M28C64 and M28C64-xxW (TA = 0 to 70 C or -40 to 85 C or -40 to 125 C; VCC = 4.5 to 5.5 V) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
Symbol tELWL tWHEH tWLWH2 tGLWH tWHRH Parameter Chip Enable Low to Write Enable Low Write Enable High to Chip Enable High Write Enable Low to Write Enable High Output Enable Low to Write Enable High Write Enable High to Write Enable Low Test Condition G = VCC + 7V G = VCC + 7V G = VCC + 7V G = VCC + 7V G = VCC + 7V Min. 1 0 10 1 3 Max. Unit s ns ms s ms
Note: 1. Sampled only, not 100% tested.
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M28C64
Table 6A. Read Mode DC Characteristics for M28C64 and M28C64-A (5V range) (TA = 0 to 70 C or -40 to 85 C or -40 to 125 C; VCC = 4.5 to 5.5 V)
Symbol ILI ILO ICC 1 ICC1 1 ICC2 1 V IL V IH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current (TTL inputs) Supply Current (CMOS inputs) Supply Current (Stand-by) TTL Supply Current (Stand-by) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 2.1 mA IOH = -400 A 2.4 Test Condi tion 0 V VIN VCC 0 V VOUT VCC E = VIL, G = VIL , f = 5 MHz E = VIL, G = VIL , f = 5 MHz E = VIH E > VCC - 0.3V -0.3 2 Min. Max. 10 10 30 25 1 100 0.8 VCC + 0.5 0.4 Unit A A mA mA mA A V V V V
Note: 1. All inputs and outputs open circuit.
Table 6B. Read Mode DC Characteristics for M28C64-xxW (3V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
Symbol ILI ILO ICC 1 ICC2 1 V IL V IH VOL VOH Parameter Input Leakage Current Output Leakage Current Supply Current (CMOS inputs) E = VIL, G = VIL , f = 5 MHz, VCC = 3.6V Supply Current (Stand-by) CMOS Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage IOL = 1.6 mA IOH = -400 A 0.8 VCC E > VCC - 0.3V -0.3 2 10 20 0.6 VCC + 0.5 0.2 VCC mA A V V V V Test Condi tion 0 V VIN VCC 0 V VOUT VCC E = VIL, G = VIL , f = 5 MHz, VCC = 3.3V Min. Max. 10 10 8 Unit A A mA
Note: 1. All inputs and outputs open circuit.
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M28C64
Table 7. Input and Output Parameters1 (TA = 25 C, f = 1 MHz)
Symbol C IN C OUT Parameter Input Capacitance Output Capacitance Test Condition V IN = 0 V VOUT = 0 V Min. Max. 6 12 Unit pF pF
Note: 1. Sampled only, not 100% tested.
Table 8. AC Measurement Conditions
Input Rise and Fall Times Input Pulse Voltages (M28C64, M28C64-A) Input Pulse Voltages (M28C64-xxW) Input and Output Timing Reference Voltages (M28C64, M28C64-A) Input and Output Timing Reference Voltages (M28C64-xxW) 20 ns 0.4 V to 2.4 V 0 V to VCC-0.3V 0.8 V to 2.0 V 0.5 VCC
Figure 8. AC Testing Input Output Waveforms
4.5V to 5.5V Operating Voltage 2.4V 2.0V 0.8V
Figure 9. AC Testing Equivalent Load Circuit
0.4V
IOL DEVICE UNDER TEST IOH CL = 100pF OUT
2.7V to 3.6V Operating Voltage VCC - 0.3V 0.5 VCC 0V
AI02101B
CL includes JIG capacitance
AI02102B
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M28C64
Table 9A. Read Mode AC Characteristics for M28C64 and M28C64-A (5V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V)
Symbol Alt. Parameter Test Condi t ion E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 M28C64 -90 Min Max 90 90 40 40 40 0 0 0 Min -12 Max 120 120 45 45 45 0 0 0 Min -15 Max 150 150 50 50 50 ns ns ns ns ns ns Unit
tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Table 9B. Read Mode AC Characteristics for M28C64 (5V range) (TA = -40 to 125 C; VCC = 4.5 to 5.5 V)
Symbol Alt. Parameter Test Condi t ion E = VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E = VIL, G = VIL 0 0 0 M28C64 -12 Min Max 120 120 45 65 65 ns ns ns ns ns ns Unit
tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
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M28C64
Table 9C. Read Mode AC Characteristics for M28C64-xxW (3V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
Symbol Alt. Parameter Test Condit ion E =VIL, G = VIL G = VIL E = VIL G = VIL E = VIL E =VIL, G = VIL 0 0 0 M28C64-xxW -12 Min -15 -20 Max 200 200 100 0 0 0 55 55 0 0 0 -25 Min Max 250 250 150 60 60 0 0 0 -30 Min Max 300 300 150 60 60 ns ns ns ns ns ns Unit
Max Min 120 120 80 45 45 0 0 0
Max Min 150 150 80 50 50
tAVQV tELQV tGLQV tEHQZ1 tGHQZ1 tAXQX
tACC tCE tOE tDF tDF tOH
Address Valid to Output Valid Chip Enable Low to Output Valid Output Enable Low to Output Valid Chip Enable High to Output Hi-Z Output Enable High to Output Hi-Z Address Transition to Output Transition
Note: 1. Output Hi-Z is defined as the point at which data is no longer driven.
Figure 10. Read Mode AC Waveforms (with Write Enable, W, high)
A0-A12 tAVQV E tGLQV G tELQV DQ0-DQ7
VALID tAXQX
tEHQZ
tGHQZ DATA OUT Hi-Z
AI00749B
Note: 1. Write Enable (W) = VIH
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M28C64
Table 10A. Write Mode AC Characteristics for M28C64 and M28C64-A (5V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 4.5 to 5.5 V)
M28C64 Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H Alt. tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tWP tBLC Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Time-out after last byte write (M28C64) Time-out after last byte write (M28C64-A) Write Cycle Time (M28C64) Write Cycle Time (M28C64-A) Write Enable High to Ready/Busy Low Chip Enable High to Ready/Busy Low Data Valid before Write Enable High Data Valid before Chip Enable High Note 1 Note 1 50 50 E = VIL, G = VIH G = VIH, W = VIL 50 0 0 0 0 0 0 50 50 100 20 3 1 150 150 1000 Test Condit ion Min E = VIL, G = VIH G = VIH, W = VIL G = VIH E = VIL W = VIL G = VIH 0 0 0 0 0 0 50 50 1 1 Max ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s s ms ms ns ns ns ns Unit
tQ5HQ5X tWHRL tEHRL tDVWH tDVEH
tWC tDB tDB tDS tDS
Note: 1. With a 3.3 k pull-up resistor.
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M28C64
Table 10B. Write Mode AC Characteristics for M28C64 (5V range) (TA = -40 to 125 C; VCC = 4.5 to 5.5 V)
M28C64 Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H Alt. tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tWP tBLC Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Time-out after last byte write (M28C64) Time-out after last byte write (M28C64-A) Write Cycle Time (M28C64) Write Cycle Time (M28C64-A) Write Enable High to Ready/Busy Low Chip Enable High to Ready/Busy Low Data Valid before Write Enable High Data Valid before Chip Enable High Note 1 Note 1 50 50 E = VIL, G = VIH G = VIH, W = VIL 50 0 0 0 0 0 0 50 50 100 20 3 1 150 150 1000 Test Condit ion Min E = VIL, G = VIH G = VIH, W = VIL G = VIH E = VIL W = VIL G = VIH 0 0 0 0 0 0 75 75 1 1 Max ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s s ms ms ns ns ns ns Unit
tQ5HQ5X tWHRL tEHRL tDVWH tDVEH
tWC tDB tDB tDS tDS
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M28C64
Table 10C. Write Mode AC Characteristics for M28C64-xxW (3V range) (TA = 0 to 70 C or -40 to 85 C; VCC = 2.7 to 3.6 V)
M28C64-xxW Symbol tAVWL tAVEL tELWL tGHWL tGHEL tWLEL tWLAX tELAX tWLDV tELDV tELEH tWHEH tWHGL tEHGL tEHWH tWHDX tEHDX tWHWL tWLWH tWLQ5H tQ5HQ5X tWHRL tEHRL tDVWH tDVEH Alt. tAS tAS tCES tOES tOES tWES tAH tAH tDV tDV tWP tCEH tOEH tOEH tWEH tDH tDH tWPH tWP tBLC tWC tDB tDB tDS tDS Parameter Address Valid to Write Enable Low Address Valid to Chip Enable Low Chip Enable Low to Write Enable Low Output Enable High to Write Enable Low Output Enable High to Chip Enable Low Write Enable Low to Chip Enable Low Write Enable Low to Address Transition Chip Enable Low to Address Transition Write Enable Low to Input Valid Chip Enable Low to Input Valid Chip Enable Low to Chip Enable High Write Enable High to Chip Enable High Write Enable High to Output Enable Low Chip Enable High to Output Enable Low Chip Enable High to Write Enable High Write Enable High to Input Transition Chip Enable High to Input Transition Write Enable High to Write Enable Low Write Enable Low to Write Enable High Time-out after the last byte write Write Cycle Time Write Enable High to Ready/Busy Low Chip Enable High to Ready/Busy Low Data Valid before Write Enable High Data Valid before Chip Enable High Note 1 Note 1 50 50 E = VIL, G = VIH G = VIH, W = VIL 100 0 0 0 0 0 0 50 100 100 5 150 150 1000 Test Condit ion Min E = VIL, G = VIH G = VIH, W = VIL G = VIH E = VIL W = VIL G = VIH 0 0 0 0 0 0 100 100 1 1 1000 Max ns ns ns ns ns ns ns ns s s ns ns ns ns ns ns ns ns ns s ms ns ns ns ns Unit
Note: 1. With a 3.3 k pull-up resistor.
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M28C64
Figure 11. Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A12 tAVWL E tELWL G tGHWL W tWLDV DQ0-DQ7 DATA IN tDVWH RB tWHRL
AI01126
VALID tWLAX
tWHEH
tWLWH
tWHGL
tWHWL
tWHDX
Figure 12. Write Mode AC Waveforms (Chip Enable, E, controlled)
A0-A12 tAVEL E tGHEL G tWLEL W tELDV DQ0-DQ7 DATA IN tDVEH RB tEHRL
AI00751
VALID tELAX
tELEH
tEHGL
tEHWH
tEHDX
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M28C64
Figure 13. Page Write Mode AC Waveforms (Write Enable, W, controlled)
A0-A12 Addr 0 Addr 1 Addr 2 Addr n
E
G tWHWL W tWLWH DQ0-DQ7 (in) Byte 0 Byte 1 Byte 2 Byte n
DQ5 (out) tWHRL RB
AI00752D
tWLQ5H tQ5HQ5X
Figure 14. Software Protected Write Cycle Waveforms
G
E tWLWH W tAVEL A0-A5 tWHDX A6-A12 1555h 0AAAh 1555h Page Address tWLAX Byte Address tWHWL
tDVWH DQ0-DQ7 AAh 55h A0h Byte 0 Byte 62 Byte 63
AI01358B
Note: 1. A12 to A6 must specify the same page address during each high-to-low transition of W (or E). G must be high only when W and E are both low.
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M28C64
Figure 15. Data Polling Sequence Waveforms
A0-A12 Address of the last byte of the Page Write instruction
E
G
W
DQ7 DQ7 DQ7 DQ7 DQ7 DQ7
LAST WRITE
INTERNAL WRITE SEQUENCE
READY
AI00753C
Figure 16. Toggle Bit Sequence Waveforms
A0-A12
E
G
W
DQ6
(1)
LAST WRITE
TOGGLE INTERNAL WRITE SEQUENCE
READY
AI00754D
Note: 1. The Toggle Bit is first set to `0'.
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M28C64
Table 11. Ordering Information Scheme
Example: M28C64 - A 12 BS 6 T
Write Time blank A1 tWC = 3 ms at 4.5V to 5.5V; tWC = 5 ms at 2.7V to 3.6V tWC = 1 ms at 4.5V to 5.5V T
Option Tape and Reel Packing
Speed 90 12 15 20 3 25 3 30 3
2
Temperature Range 1 6 3 0 C to 70 C -40 C to 85 C -40 C to 125 C5
90 ns 120 ns 150 ns 200 ns 250 ns 300 ns
Package BS PDIP28 PLCC32 SO28 (300 mil width) TSOP28 (8 x 13.4 mm)
Operating Voltage blank 4.5 V to 5.5 V W4
Note: 1. 2. 3. 4. 5.
KA MS NS
2.7 V to 3.6 V
Available only with 120 ns speed (-12), 5V operating range (-blank), and -40 to 85 C temperature range (-6). Available for the M28C64 only. Available for the 3V range (-xxW) only. Not available for the 1 ms write time option (-A). Available only for the "M28C64 - 12 MS 3" (5V range, SO28 package)
ORDERING INFORMATION Devices are shipped from the factory with the memory content set at all `1's (FFh). The notation used for the device number is as shown in Table 11. For a list of available options (speed, package, etc.) or for further information on any aspect of this device, please contact your nearest ST Sales Office.
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M28C64
Table 12. PDIP28 - 28 pin Plastic DIP, 600 mils width
mm Symb. Typ. A A1 A2 B B1 C D E E1 e1 eA L S N 2.54 Min. 3.94 0.38 3.56 0.38 1.14 0.20 34.70 14.80 12.50 - 15.20 3.05 1.02 0 28 Max. 5.08 1.78 4.06 0.56 1.78 0.30 37.34 16.26 13.97 - 17.78 3.82 2.29 15 0.100 Typ. Min. 0.155 0.015 0.140 0.015 0.045 0.008 1.366 0.583 0.492 - 0.598 0.120 0.040 0 28 Max. 0.200 0.070 0.160 0.021 0.070 0.012 1.470 0.640 0.550 - 0.700 0.150 0.090 15 inches
Figure 17. PDIP28 (BS)
A2 A1 B1 B D2 D S
N
A L eA eB C
e1
E1
1
E
PDIP
Note: 1. Drawing is not to scale.
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M28C64
Table 13. PLCC32 - 32 lead Plastic Leaded Chip Carrier, rectangular
Symbol A A1 A2 B B1 D D1 D2 E E1 E2 e F R N Nd Ne CP 0.89 1.27 mm Typ. Min. 2.54 1.52 - 0.33 0.66 12.32 11.35 9.91 14.86 13.89 12.45 - 0.00 - 32 7 9 0.10 Max. 3.56 2.41 0.38 0.53 0.81 12.57 11.56 10.92 15.11 14.10 13.46 - 0.25 - 0.035 0.050 Typ. inches Min. 0.100 0.060 - 0.013 0.026 0.485 0.447 0.390 0.585 0.547 0.490 - 0.000 - 32 7 9 0.004 Max. 0.140 0.095 0.015 0.021 0.032 0.495 0.455 0.430 0.595 0.555 0.530 - 0.010 -
Figure 18. PLCC (KA)
D D1
1N
A1 A2
B1
Ne
E1 E
F 0.51 (.020)
D2/E2 B
e
1.14 (.045)
Nd
A R CP
PLCC
Note: 1. Drawing is not to scale.
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M28C64
Table 14. SO28 - 28 lead Plastic Small Outline, 300 mils body width
mm Symb. Typ. A A1 A2 B C D E e H L N CP 1.27 Min. 2.46 0.13 2.29 0.35 0.23 17.81 7.42 - 10.16 0.61 0 28 0.10 Max. 2.64 0.29 2.39 0.48 0.32 18.06 7.59 - 10.41 1.02 8 0.050 Typ. Min. 0.097 0.005 0.090 0.014 0.009 0.701 0.292 - 0.400 0.024 0 28 0.004 Max. 0.104 0.011 0.094 0.019 0.013 0.711 0.299 - 0.410 0.040 8 inches
Figure 19. SO28 wide (MS)
A2 B e D
A C CP
N
E
1
H A1 L
SO-b
Note: 1. Drawing is not to scale.
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M28C64
Table 15. TSOP28 - 28 lead Plastic Thin Small Outline, 8 x 13.4 mm
mm Symb. Typ. A A1 A2 B C D D1 E e L N CP 0.55 0.95 0.17 0.10 13.20 11.70 7.90 - 0.50 0 28 0.10 Min. Max. 1.25 0.20 1.15 0.27 0.21 13.60 11.90 8.10 - 0.70 5 0.022 0.037 0.007 0.004 0.520 0.461 0.311 - 0.020 0 28 0.004 Typ. Min. Max. 0.049 0.008 0.045 0.011 0.008 0.535 0.469 0.319 - 0.028 5 inches
Figure 20. TSOP28 (NS)
A2
1 N
e E B
N/2
D1 D
A CP
DIE
C
TSOP-a
A1
L
Note: 1. Drawing is not to scale.
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M28C64
Table 16. Revision History
Date 31-Mar-2000 19-Jun-2000 Description of Revision -40 to 125C temperature range added to timing and characteristics tables, and order info Paragraph on behaviour, following an out-of-bounds page write operation, corrected
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M28C64
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express writt en approval of STMicroelectronics. (c) 2000 STMicroelectronics - All Rights Reserved The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www. st.com
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